In Universal Verification Methodology (UVM), controlling the amount of information printed during simulation is critical for both debugging and performance. Too little output can hide important issues, while too much verbosity can overwhelm logs and slow down analysis. This is why many verification engineers want to understand how to pass UVM verbosity from command line instead of hardcoding it in the testbench. Command-line control provides flexibility, saves time, and allows the same test to be reused in different debugging scenarios.
Understanding UVM Verbosity
UVM verbosity determines which messages are displayed during simulation. UVM provides different verbosity levels that help engineers filter messages based on importance.
These verbosity levels allow you to control informational messages without changing the source code.
Common UVM Verbosity Levels
- UVM_NONE
- UVM_LOW
- UVM_MEDIUM
- UVM_HIGH
- UVM_FULL
- UVM_DEBUG
Each level includes all messages from lower levels. Higher verbosity gives more detailed insight into internal behavior.
Why Use Command Line Verbosity Control
Hardcoding verbosity in the testbench limits flexibility. When verbosity is passed from the command line, engineers can adjust output without recompiling or modifying code.
This is especially useful in regression testing, debugging intermittent failures, and sharing testbenches across teams.
How UVM Handles Verbosity Internally
UVM messages are printed using macros such as uvm_info, uvm_warning, and uvm_error. Each message includes a verbosity level.
During simulation, UVM compares the message verbosity with the current verbosity setting to decide whether to print it.
Passing UVM Verbosity from Command Line
The most common way to pass UVM verbosity from command line is by using plusargs. Plusargs are command-line arguments that UVM reads during runtime.
Basic Plusarg Syntax
UVM recognizes verbosity-related plusargs automatically when simulation starts.
+UVM_VERBOSITY=UVM_HIGHThis argument sets the global verbosity level to UVM_HIGH.
Global Versus Component-Level Verbosity
UVM supports both global and component-specific verbosity control.
Global verbosity affects all components unless overridden.
Global Verbosity Example
+UVM_VERBOSITY=UVM_MEDIUMThis ensures that only messages with UVM_MEDIUM or lower are displayed.
Setting Verbosity for Specific Components
Sometimes you only want detailed output from a specific component such as an agent or scoreboard.
UVM allows this using component-specific verbosity settings.
Component-Specific Command Line Syntax
+uvm_set_verbosity=uvm_test_top.env.agent,UVM_HIGHThis sets the verbosity of a specific component without affecting the rest of the testbench.
Understanding the uvm_set_verbosity Plusarg
The uvm_set_verbosity plusarg is very powerful. It allows fine-grained control over simulation output.
General Format
+uvm_set_verbosity=<component_path>,<verbosity>,<phase>,<time>Not all fields are mandatory, but they provide advanced control when needed.
Using Verbosity with UVM Tests
Different tests often require different verbosity levels.
Passing verbosity from the command line allows you to reuse the same test across multiple debug levels.
Example with Test Selection
+UVM_TESTNAME=my_test +UVM_VERBOSITY=UVM_FULLThis combination selects the test and sets the verbosity in one command.
Simulator Support for UVM Verbosity
Most major simulators support UVM verbosity plusargs consistently.
While syntax may vary slightly, the general concept remains the same.
Common Mistakes When Passing Verbosity
Many issues arise from simple mistakes.
- Using incorrect verbosity names
- Misspelling plusargs
- Incorrect component paths
Double-checking these details saves debugging time.
How to Verify That Verbosity Is Applied
To confirm that verbosity is working, include messages at different verbosity levels in your code.
If only certain messages appear, the verbosity filter is functioning correctly.
Combining Verbosity with Other Debug Options
Verbosity is often used alongside other debug techniques such as assertions and waveforms.
Command-line control allows engineers to enable or disable verbosity without impacting these tools.
Verbosity in Regression Testing
In large regressions, low verbosity is preferred for performance and log size.
For failing tests, rerunning with higher verbosity provides deeper insight.
Performance Impact of High Verbosity
High verbosity can slow simulations and produce large log files.
This is why it should be used selectively and controlled externally.
Best Practices for UVM Verbosity
- Use UVM_LOW for essential messages
- Reserve UVM_DEBUG for deep debugging
- Control verbosity from the command line
- Avoid hardcoding verbosity values
Why Command Line Control Is Preferred
Passing UVM verbosity from command line separates configuration from implementation.
This makes testbenches cleaner and easier to maintain.
Scalability in Large Projects
As projects grow, managing verbosity manually becomes impractical.
Command-line control scales well across teams and environments.
Debugging Workflow Improvement
Engineers can quickly adjust verbosity without recompiling.
This speeds up iteration and improves productivity.
Learning Curve for Beginners
For newcomers to UVM, verbosity control may seem complex at first.
Once understood, it becomes one of the most valuable debugging tools.
Consistency Across Simulations
Using command-line verbosity ensures consistent behavior across runs.
This is especially useful when sharing logs with teammates.
Learning how to pass UVM verbosity from command line is an essential skill for effective verification work. By using plusargs such as UVM_VERBOSITY and uvm_set_verbosity, engineers can control simulation output dynamically without modifying source code. This approach improves flexibility, supports scalable regression testing, and enhances debugging efficiency. With proper use of verbosity levels, UVM simulations become clearer, faster, and far more manageable in both small and large verification environments.